EagleSoC Board Features

The Power System and Analog System on the PSoC 5LP

Cypress PSoC 5LP chips provide isolated power and ground pins for the analog and digital blocks. These chips also come with their I/O pins separated into four power groups: V_ddio0, V_ddio1, V_ddio2, and V_ddio3. Each V_ddio pin powers a specific set of I/O pins as shown in Table 2. (The USBIOs P15[7:6] are powered from the V_ddd) This design allows PSoC 5LP to support different voltage levels on interfaces with other devices, which eliminates the need for the level-shifter device(s) on the PCB.

Figure 4: The Block Diagram of PSoC 5LP

Table 2: PSoC 5LP Power Domain and Port Pin Associations

Power Domain		Associated Power Pins	Associated Return Pins
Analog		V_DDA	V_SSA
Digital		V_DDD	V_SSD
I/O Pins	P0[7:0] P4[7:0] P12 [3:2]	V_DDIO0	V_SSA
	P1[7:0] P5[7:0] P12[7:6]	V_DDIO1	V_SSD
	P2 [7:0] P6[7:0] P12[5:4] P15[5:4]	V_DDIO2	V_SSD
	P3[7:0] P12[1:0] P15[3:0]	V_DDIO3	V_SSA
	P15[7:6] (USB)	V_DDD	V_SSD

PSoC 5LP Internal Analog Routing

PSoC 5LP can be divided into analog and digital sections as shown in Figure 5. The top section of the silicon is mostly analog and the bottom section is digital. The analog section consists of several analog blocks such as a Delta-Sigma ADC (DSM), comparators, DACs, and SC/CT blocks. The digital section contains the CPU, RAM, ROM, DAM, UDBs, Clocks, and so on.

The entire PSoC 5LP chip is surrounded by pins. Most of these pins are GPIO pins. The GPIO pins can be configured for eight different modes: seven digital and one analog input/output mode.

PSoC 5LP uses Analog Globals (AG) and Analog Mux Buses (AMUXBUS) to connect GPIOs and the various analog blocks. The PSoC 5LP devices are divided into four quadrants (upper left, upper right, lower left, and lower right), and two sides (left and right side) as shown in Figure 5. The analog global bus has 16 routes and it is divided into four groups: AGR[7:4], AGR[3:0], AGL[7:4], and AGL[3:0]. There are two AMUXBUS routes in the PSoC 5LP device and AMUXBUSes are also divided into two sides: AMUXBUSL on the left side and AMUXBUSR on the right side.

Best Analog Ports

PSoC 5LP families have several ports that can be used for analog input and output. From Figure 5, you can see that the upper section has shorter connection path between the analog blocks and GPIO pins. Therefore, the full 8-pin ports that reside in the analog upper section of the chip have a slight analog performance advantage P0[7:0], P3[7:0], and P4[7:0]. The analog global buses, AGL[7:4} and AGR[7:4] that connect to these ports, also reside only in the upper analog section of the part, which gives these ports a slight signal-to-noise ratio advantage.

PSoC5LP AnalogDigitalLayout s
Figure 5: PSoC 5LP Analog/Digital layout

Separating Analog and Digital Signals

Depending on the sensor or signal source that you use in your project, most analog signals tend to be relatively high impedance, at times as high as several mega-ohms. Digital signals on the other hand are usually low impedance on the order of 10 to 50 ohms with fast edge times of tens of nanoseconds or faster.

When these two signals are placed in close proximity on a circuit board or are on adjacent pins, the fast rise and fall times of the digital signal can easily be capacitively coupled to the analog signal. Therefore, when selecting pins for analog and digital functions, it is recommended that analog and high-speed digital signals be kept away from each other whenever possible. This coupling can occur both internal to the chip at the I/O pads and on the circuit board traces. Isolating these signals by at least one pin reduces this coupling both internally and externally. If possible it is a good design practice to keep analog and digital signals on opposite sides of the chip. This also helps when it is time to layout the circuit board.

A few easy steps can be used to plan a pinout for optimal analog performance.

Design Steps

Determine how many analog pins/ports are required for a given design.
Determine which signals can or should use the dedicated routes between the analog block and the GPIO pin, Make these pin assignments first.
Start with port 0 and work out in both directions to port 4 and port 3 and select the analog GPIO pins needed for the design.
Draw a line between the analog GPIO pins selected and the rest of the pins required for the design.
Keep all analog GPIOs on one side of the line and all digital GPIOs on the other,

Follow these simple steps to isolate the analog and digital signals on both the chip and your circuit board.

EagleSoC Boards

EagleSoC boards fully support PSoC 5LP power features and provide separate return paths on analog and digital sections. Each EagleSoC board can be divided into two sections: upper and lower sections. If your project only has digital signals, both sections can be used. If your project has analog and digital signals, then the upper section is used for digital signals and the lower section is used for analog signals.

EagleSoC Develop Board
EagleSoC Mini Board

EagleSoC Develop Board
EagleSoC Mini Board

EagleSoC Develop Board

In the EagleSoC Development Board, the upper section is designed to support digital signals, the P1[7:5, 2], P2[7:0], P5[7:0], P6[7:0], P12[7:4], and P15[5:4] reside in the upper section. Each upper section header has one power source pin (V_ddio1 for P1, P5, and P12[7:6]; V_ddio2 for P2, P6, P12[5:4] and P15[4,5]), and one digital ground pin (V_ssd). The lower section is designed to support either analog or digital signals and consists of P0[7:0], P3[7:0], and P4[7:0]. Each lower section header has one power source pin (V_ddio0 for P0 and P4; V_ddio3 for P3), and each pin has one analog return ground pin (V_ssa).

Figure 6: EagleSoC Board is Designed for Analog/Digital Mixed-Signal Applications

EagleSoC Mini Board

In the EagleSoC Mini Board, the upper section is designed to support digital signals, the P1[7:5, 2], P2[7:0], P12[7:4] and P15[5:4] reside in the upper section. Each upper section header has one power source pin (V_ddio1 for P1, P15, and P12[7:6]. V_ddio2 for P2, P12[5:4], and P15[5:4]), and one digital ground pin (V_ssd). The lower section is designed to support either analog or digital signals, and consists of P0[7:0], P3[7:0], and P12[3:0]. Each lower section header has one power source pin (V_ddio0 for P0 and P12[3:2]; V_ddio3 for P3 and P12[1:0]), and each pin has one analog return ground pin (V_ssa).

Figure 7: EagleSoC Mini Board is also Designed for Analog/Digital Mixed-Signal Applications