EagleSoC Board Features
The Power System and Analog System on the PSoC 5LP
Cypress PSoC 5LP chips provide isolated power and ground pins for the analog and digital blocks. These chips also come with their I/O pins separated into four power groups: Vddio0, Vddio1, Vddio2, and Vddio3. Each Vddio pin powers a specific set of I/O pins as shown in Table 2. (The USBIOs P15[7:6] are powered from the Vddd) This design allows PSoC 5LP to support different voltage levels on interfaces with other devices, which eliminates the need for the level-shifter device(s) on the PCB.
Figure 4: The Block Diagram of PSoC 5LP
|Power Domain||Associated Power Pins||Associated Return Pins|
PSoC 5LP Internal Analog Routing
PSoC 5LP can be divided into analog and digital sections as shown in Figure 5. The top section of the silicon is mostly analog and the bottom section is digital. The analog section consists of several analog blocks such as a Delta-Sigma ADC (DSM), comparators, DACs, and SC/CT blocks. The digital section contains the CPU, RAM, ROM, DAM, UDBs, Clocks, and so on.
The entire PSoC 5LP chip is surrounded by pins. Most of these pins arepins. The GPIO pins can be configured for eight different modes: seven digital and one analog input/output mode.
PSoC 5LP uses Analog Globals (AG) and Analog Mux Buses (AMUXBUS) to connect GPIOs and the various analog blocks. The PSoC 5LP devices are divided into four quadrants (upper left, upper right, lower left, and lower right), and two sides (left and right side) as shown in Figure 5. The analog global bus has 16 routes and it is divided into four groups: AGR[7:4], AGR[3:0], AGL[7:4], and AGL[3:0]. There are two AMUXBUS routes in the PSoC 5LP device and AMUXBUSes are also divided into two sides: AMUXBUSL on the left side and AMUXBUSR on the right side.
Best Analog Ports
PSoC 5LP families have several ports that can be used for analog input and output. From Figure 5, you can see that the upper section has shorter connection path between the analog blocks and GPIO pins. Therefore, the full 8-pin ports that reside in the analog upper section of the chip have a slight analog performance advantage P0[7:0], P3[7:0], and P4[7:0]. The analog global buses, AGL[7:4} and AGR[7:4] that connect to these ports, also reside only in the upper analog section of the part, which gives these ports a slight signal-to-noise ratio advantage.
Figure 5: PSoC 5LP Analog/Digital layout