Mixed-Signal Design
When you design an embedded system with mixed-signal or high-precision ADCs, you must consider the path of the current flow inside of the PCB. Trace currents of just a few milliamperes can be high enough to cause significant problems for analog signals. To better understand this problem, we should know the minimum voltage level that an ADC can resolve. In other words, we need to calculate the ADC resolution. An 8-bit ADC results in 256 possible digital output values. For a range of 2V signals, the minimum value that can be detected by an 8-bit ADC (or ADC voltage resolution) is 2 V/(256-1) = 0.008V or about 8 mV. From Table 1, we can observe that the ADC voltage resolution will become smaller and smaller when we increase the bits-resolution of ADC. When the resolution is 20-bits, an ADC resolves down to 2 μV.
Table 1: ADC Resolution
| Range ± 1.024 Volts | ||
| ADC Bits | Resolution | Units |
| 8 | 8 | mV |
| 10 | 2 | mV |
| 12 | 500 | μV |
| 16 | 31.3 | μV |
| 20 | 2 | μV |
Offsets and noise sources below 1 mV, which were insignificant with a low-resolution ADC, are now significant when using a 12- to 20-bit ADC. These errors can easily be overlooked by designers who are not used to sensitive analog circuits.
How Current Return Paths Affect Signal
Analog and Digital Devices Share Same Return Path Outside of Board
Trace resistance usually causes a problem when a sensitive analog signal's return path is shared with a digital or a high-current analog device. Figure 1 shows an example where return current paths are shared between the analog and digital ground, and between a sensor and an LED device. Both of these shared paths can cause problems that may appear as system offsets or gain errors.
Figure 1: Resistance in Signal Return Path
From equations (1) and (2), you can see how the current on the LED (ILED) affects the voltage, VMEAS. When the VSENSOR value is very small, then ILED will have a significant influence on the result of voltage VMEAS.
When the ADC in this example measures the output of the sensor, it also measures the voltage across the trace resistance (RT1+RT2+RT3). Depending on the length of the trace between the common ground point and the place where the sensor and LED currents combine, there is a significant dependency on the desired accuracy of the system, the voltage gain of the sensor, and the magnitude of the offset error voltage.
Analog and Digital Ground are connected together on the PCB
Most of the embedded boards do not have separate analog and digital signal ground on their PCBs. The analog ground (VSSA) is as important as any of the signals you are measuring. Sharing the trace between the microcontroller analog ground pin and digital ground with any component that uses even a few hundred microamperes can cause problems when measuring sub-millivolt signals. In Figure 2, the LED's current flows (ILED) in the same path back to the power supply, but the sensor has its own path. The internal band-gap reference is also connected to VSSA. Any voltage induced by sharing the return path with the LED causes the ADC's reference to fluctuating by the (ILED x Rt3) drop. This offset between the reference and VSSA causes an ADC gain error.
Figure 2: Current in Analog Ground Path
From equation (3), you can see that the current on the LED (ILED) still affects the voltage, VMEAS. When the VSENSOR value is very small, then ILED will have a significant influence on the result of voltage VMEAS.
Analog and Digital Ground are Separated (EagleSoC Solution)
Proper design practice is to provide separate ground paths for the digital ground (VSSD) and analog ground (VSSD). There are no shared return paths for the sensor and LED as shown in Figure 3. The sensor, ADC, and Vref are at the same analog ground reference, so changing current in the LED has little or no effect on the sensor's analog output.
Figure 3: Separates Analog and Digital Ground Paths
Equation (4) shows, that there is no effect on VMeas from the LED device because the current from digital signals is traveling through its own ground path to the power ground plane.
The Power System and Analog System on the PSoC 5LP
Cypress PSoC 5LP chips provide isolated power and ground pins for the analog and digital blocks. These chips also come with their I/O pins separated into four power groups: Vddio0, Vddio1, Vddio2, and Vddio3. Each Vddio pin powers a specific set of I/O pins as shown in Table 2. (The USBIOs P15[7:6] are powered from the Vddd) This design allows PSoC 5LP to support different voltage levels on interfaces with other devices, which eliminates the need for the level-shifter device(s) on the PCB.
PSoC 5LP Internal Analog Routing
PSoC 5LP can be divided into analog and digital sections as shown in Figure 5. The top section of the silicon is mostly analog and the bottom section is digital. The analog section consists of several analog blocks such as a Delta-Sigma ADC (DSM), comparators, DACs, and SC/CT blocks. The digital section contains the CPU, RAM, ROM, DAM, UDBs, Clocks, and so on.
The entire PSoC 5LP chip is surrounded by pins. Most of these pins are GPIO pins. The GPIO pins can be configured for eight different modes: seven digital and one analog input/output mode.
PSoC 5LP uses Analog Globals (AG) and Analog Mux Buses (AMUXBUS) to connect GPIOs and the various analog blocks. The PSoC 5LP devices are divided into four quadrants (upper left, upper right, lower left, and lower right), and two sides (left and right side) as shown in Figure 5. The analog global bus has 16 routes and it is divided into four groups: AGR[7:4], AGR[3:0], AGL[7:4], and AGL[3:0]. There are two AMUXBUS routes in the PSoC 5LP device and AMUXBUSes are also divided into two sides: AMUXBUSL on the left side and AMUXBUSR on the right side.
Best Analog Ports
PSoC 5LP families have several ports that can be used for analog input and output. From Figure 5, you can see that the upper section has shorter connection path between the analog blocks and GPIO pins. Therefore, the full 8-pin ports that reside in the analog upper section of the chip have a slight analog performance advantage P0[7:0], P3[7:0], and P4[7:0]. The analog global buses, AGL[7:4} and AGR[7:4] that connect to these ports, also reside only in the upper analog section of the part, which gives these ports a slight signal-to-noise ratio advantage.
Figure 5: PSoC 5LP Analog/Digital layout
Separating Analog and Digital Signals
Depending on the sensor or signal source that you use in your project, most analog signals tend to be relatively high impedance, at times as high as several mega-ohms. Digital signals on the other hand are usually low impedance on the order of 10 to 50 ohms with fast edge times of tens of nanoseconds or faster.
When these two signals are placed in close proximity on a circuit board or are on adjacent pins, the fast rise and fall times of the digital signal can easily be capacitively coupled to the analog signal. Therefore, when selecting pins for analog and digital functions, it is recommended that analog and high-speed digital signals be kept away from each other whenever possible. This coupling can occur both internal to the chip at the I/O pads and on the circuit board traces. Isolating these signals by at least one pin reduces this coupling both internally and externally. If possible it is a good design practice to keep analog and digital signals on opposite sides of the chip. This also helps when it is time to layout the circuit board.
A few easy steps can be used to plan a pinout for optimal analog performance.
Design Steps
- Determine how many analog pins/ports are required for a given design.
- Determine which signals can or should use the dedicated routes between the analog block and the GPIO pin, Make these pin assignments first.
- Start with port 0 and work out in both directions to port 4 and port 3 and select the analog GPIO pins needed for the design.
- Draw a line between the analog GPIO pins selected and the rest of the pins required for the design.
- Keep all analog GPIOs on one side of the line and all digital GPIOs on the other,
Follow these simple steps to isolate the analog and digital signals on both the chip and your circuit board.
EagleSoC Boards
EagleSoC boards fully support PSoC 5LP power features and provide separate return paths on analog and digital sections. Each EagleSoC board can be divided into two sections: upper and lower sections. If your project only has digital signals, both sections can be used. If your project has analog and digital signals, then the upper section is used for digital signals and the lower section is used for analog signals.
EagleSoC Develop Board
In the EagleSoC Development Board, the upper section is designed to support digital signals, the P1[7:5, 2], P2[7:0], P5[7:0], P6[7:0], P12[7:4], and P15[5:4] reside in the upper section. Each upper section header has one power source pin (Vddio1 for P1, P5, and P12[7:6]; Vddio2 for P2, P6, P12[5:4] and P15[4,5]), and one digital ground pin (Vssd). The lower section is designed to support either analog or digital signals and consists of P0[7:0], P3[7:0], and P4[7:0]. Each lower section header has one power source pin (Vddio0 for P0 and P4; Vddio3 for P3), and each pin has one analog return ground pin (Vssa).
Figure 6: EagleSoC Board is Designed for Analog/Digital Mixed-Signal Applications
EagleSoC Mini Board
In the EagleSoC Mini Board, the upper section is designed to support digital signals, the P1[7:5, 2], P2[7:0], P12[7:4] and P15[5:4] reside in the upper section. Each upper section header has one power source pin (Vddio1 for P1, P15, and P12[7:6]. Vddio2 for P2, P12[5:4], and P15[5:4]), and one digital ground pin (Vssd). The lower section is designed to support either analog or digital signals, and consists of P0[7:0], P3[7:0], and P12[3:0]. Each lower section header has one power source pin (Vddio0 for P0 and P12[3:2]; Vddio3 for P3 and P12[1:0]), and each pin has one analog return ground pin (Vssa).
Figure 7: EagleSoC Mini Board is also Designed for Analog/Digital Mixed-Signal Applications